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IDT74LVCH16701A 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
* Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * All inputs, outputs, and I/O are 5V tolerant * Supports hot insertion * Available in SSOP, TSSOP, and TVSOP packages
IDT74LVCH16701A
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
* High Output Drivers: 24mA * Reduced system switching noise
The LVCH16701A 18-bit read/write buffer is built using advanced dual metal CMOS technology. The device is designed as an 18-bit read/write buffer with a four deep FIFO and a read-back latch. It can be used as a read/ write buffer between a CPU and a memory or to interface a high-speed bus and a slow peripheral. The A-to-B (write) path has a four deep FIFO for pipelined operations. The FIFO can be reset and a FIFO full condition is indicated by the full flag (FF). The B-to-A (read) path has a latch. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCH16701A has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The LVCH16701A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
A1-18
3
18
27
OEBA
RESET CLK WCE RCE FF
29 55 Q 2 56 30
FIFO (4 deep)
LATCH
D
LE
28
LE
OEAB
1
18
54
B1-18
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4233/3
IDT74LVCH16701A 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND -0.5 to +6.5 -65 to +150 -50 to +50 -50 100 TSTG IOUT IIK IOK ICC ISS
Unit V C mA mA mA
OEAB WCE A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LE
RCE CLK B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 FF RESET
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
NOTE: 1. As applicable to the device type.
SSOP/ TSSOP/ TVSOP TOP VIEW
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IDT74LVCH16701A 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Names A1-18 B1-18 CLK WCE RCE FF RESET OEAB OEBA LE I/O I/O I/O I I I O I I I I 18 bit I/O port (1) 18 bit I/O port (1) Clock for write path FIFO. Clocks data into FIFO when WCE is low, clocks data out of FIFO when RCE is low. When FIFO is full all further writes to the FIFO are inhibited. When FIFO is empty all reads from the FIFO are inhibited. CLK also resets the FIFO when RESET is low. Enable pin for FIFO input clock (Active LOW) Enable pin for FIFO output clock (Active LOW) Write path FIFO full flag. Goes low when FIFO is full. Synchronous FIFO reset - when low CLK resets the FIFO. The FIFO pointers are initialized to the "empty" condition and FIFO output is forced high (all ones). The FIFO full flag (FF) will be high immediately after reset. (Active LOW) Output Enable pin for B port (Active LOW) Output Enable pin for A port (Active LOW) Read path latch enable pin. When high, data flows transparently from B port to A port, B data is latched on the falling edge of LE. (Note: LE is independent of CLK and data)
NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
Description
FUNCTION TABLE(1)
Inputs OEBA H L L H H L OEAB H H H H L L LE H H L X X L RESET H H H H H H CLK Q (B) Bus Hold
(2) (2) (2) (2)
Outputs Ax Q (B) Bus Hold B to A Qo(B) Q (A) Bus Hold Q(2)(B) Bus Hold A to B - 4 CLKS Q (B) - 4 CLKS Bus Hold Case not recommended
(2)
Bx Q (A) -4CLKS Bus Hold
Notes Transparent Mode
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition 2. Level of Q before the indicated steady-state input conditions were established.
FUNCTIONAL DESCRIPTION
remains at the output of the FIFO. The FIFO may be reset by the synchronous RESET input. This resets the read and write pointers to the original "empty" condition and also sets all B outputs = 1. Simultaneous read and write attempts (clock data into FIFO as well as clock data out of FIFO) are possible except on FIFO empty and full boundaries. When the FIFO The four deep FIFO uses one clock with two clock enable pins, WCE and is empty, and a simultaneous read and write is attempted, the read is ignored RCE to clock data in and out. The FIFO has an external full flag which goes while the write is executed. If the same is attempted when the FIFO is full, LOW when the FIFO is full. Internal read and write pointers keep track of the write is ignored while the read is executed. Normal operation of the four the words stored in the FIFO. A write attempt to a full FIFO is ignored. An deep FIFO in the write path is independent of the read path operation. attempt to read from an empty FIFO will have no effect and the last read data
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This device is useful as a read/write buffer for modular high end designs. It provides multi-level buffering in the write path and single deep buffering in the read path, and is suited to write back cache implementation. The read path provides a transparent latch.
IDT74LVCH16701A 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
TIMING DIAGRAM
WRITE CYCLES
Cycle 1 CLK Cycle 2 Cycle 3 Cycle 4 Cycle 1
READ CYCLES
Cycle 2 Cycle 3 Cycle 4
RESET
WCE
OEAB
A [1:18] FF
WORD 1
WORD 2
WORD 3
WORD 4
B [1:18] RCE
WORD 1
WORD 2
WORD 3
WORD 4
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- -- -- -- -- -- -0.7 100 -- -- -- 50 -1.2 -- 10 10 500 A V mV A VCC = 3.6V VO = 0 to 5.5V -- -- 10 A Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 5 A V Unit V
Quiescent Power Supply Current Variation
3.6 VIN 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND
A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
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IDT74LVCH16701A 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 -- -- --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD CPD CPD Parameter Power Dissipation WCE Mode, OEAB = 0 Power Dissipation RCE Mode, OEBA = 0 Registered Channel (B to A) Power Dissipation OEBA = 0; CE = 0 Registered Channel Power Dissipation OEBA = 0; CE = 1 Test Conditions CL = 0pF, f = 10Mhz Typical Unit pF
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IDT74LVCH16701A 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 19 20 Parameter B1-18 to A1-18 LE (LOW to HIGH) to A1-18 CLK to FF CLK to B1-18 Output Skew(2) A1-18 to CLK (LOW to HIGH) Setup A1-18 to CLK (LOW to HIGH) Hold B1-18 to LE (HIGH to LOW) Setup B1-18 to LE (HIGH to LOW) Hold WCE, RCE (LOW) to CLK Setup WCE, RCE (LOW) to CLK Hold RESET (LOW) to CLK Setup RESET (LOW) to CLK Hold OEBA LOW to A1-18 Enable OEBA HIGH to A1-18 Disable OEBA LOW to B1-18 Enable OEBA HIGH to B1-18 Disable CLK HIGH or LOW Pulse Width LE HIGH Pulse Width Clock Frequency Clock Cycle Time 12 Test Conditions Read path/latch Read path/latch Write path Write path Write path Write path Write path Read path/latch Read path/latch Write path Write path Write path Write path Write path Write path Read path Read path Write path Read path/latch Min. Max. PROPAGATION DELAYS 2 2 1.5 1.5 -- 1.5 0.9 1.2 1 3.5 0 1.8 0.6 1.5 1.5 1.5 1.5 5 5 4.5 4.8 6 6 1 -- -- -- -- -- -- -- -- 6 5.7 6 5.7 -- -- 83 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns VCC = 3.3V 0.3V Min. Max. Unit
SETUP & HOLD TIMES
ENABLE & DISABLE TIMES
MINIMUM PULSE WIDTHS
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74LVCH16701A 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse (1, 2) Generator VIN D.U.T. RT 500 CL
LVC Link
SAME PHASE INPUT TRANSITION
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
tPHL
6 2.7 1.5 300 300 50
tPHL
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
LVC Link
VOUT
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2
LVC Link
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
Set-up, Hold, and Release Times
INPUT
tPLH1
tPHL1
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
OUTPUT 1
tSK (x)
tSK (x)
VT
LVC Link
OUTPUT 2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74LVCH16701A 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5V TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
X LVC IDT XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package
PV PA PF
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package
701A 18-Bit Read/Write Buffer 16 H 74 Double-Density, 24mA Bus-hold -40C to +85C
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